1. Field of the Invention
The present invention relates to a voltage generation circuit for internally generating a voltage at a desired voltage level. In particular, the present invention relates to a configuration of a power supply circuit generating for an internal power supply voltage differing in voltage level from an external power supply voltage through use of charge pumping operation of a capacitance element.
2. Description of the Background Art
A voltage at a different voltage level from that of a voltage provided from a system power supply is often required in semiconductor devices. For example, in a nonvolatile memory, a positive voltage and a negative voltage are required for programming and erasing data. In a display device, a positive voltage or a negative voltage is transmitted onto a gate line for selecting a pixel displaying element such as a liquid-crystal element. In these cases, a voltage (internal voltage) at a required voltage level is generated from an available power supply voltage in the semiconductor device and is supplied as a power supply voltage to an internal circuit. The internal circuit uses this internal voltage as an operating power supply voltage to drive an associated signal line or node to the level of the internal voltage.
An internal voltage generation circuit for generating an internal voltage from an externally supplied power supply voltage is generally configured of a charge pump circuit using charge pump operation of a capacitance element. In the charge pump circuit, positive or negative charges are supplied to an electrode node of the capacitance element according to a repetitive signal such as a clock signal and charged positive or negative charges are transferred to an output node to generate an internal voltage at a desired positive or negative voltage level. Such an internal voltage generation circuit using the charge pump operation of the capacitance element is widely employed as an internal power supply circuit for a driving circuit of a display device and an integrated circuit.
The internal power supply circuit or internal voltage generation circuit is required, in view of a stable operation of a load circuit consuming the internal voltage such as an internal circuit, to supply a voltage at a stable and constant voltage level to the load circuit. In order to stabilize the voltage level, a configuration as described below is usually employed for the internal power supply circuit or internal voltage generation circuit. Specifically, the level of an output voltage of the charge pump circuit is monitored and the charge pump operation is selectively activated according to the result of monitoring. Through the selective activation of the charge pump operation, charges are supplied when the absolute value of the internal voltage becomes smaller than a target voltage, to maintain the internal voltage at the target voltage level.
For monitoring the voltage level as described above, a comparison circuit is usually employed which compares a reference voltage with the output voltage of the charge pump circuit. According to an output signal of this comparison circuit, activation/inactivation of the charge pump operation is controlled. The reference voltage level is set to a constant voltage level independent of temperature and manufacturing parameters, so that the level of the internal voltage (internal power supply voltage) produced by the charge pump circuit can stably be maintained at a voltage level determined by the reference voltage.
As the comparison circuit for detecting the voltage level of the internal voltage, a differential amplifier (operational amplifier) may possibly be used. The differential amplifier includes a differential stage receiving the reference voltage and the internal voltage and a current mirror stage setting a drive current of the differential stage. A difference in conductance occurs between paired transistors of the differential stage according to the difference between the internal voltage and the reference voltage, and the level of the output voltage is determined by the difference in conductance and the charging or discharging drive current produced by the current mirror stage.
In the case where the paired transistors of the differential stage are formed of MOS transistors (insulated gate field effect transistors), the amount of the drive current for the paired transistors of the differential stage is mainly determined by the gate-to-source voltage on the condition that the threshold voltages are identical to each other. Thus, between the paired transistors of the differential stage, a difference in amount of drive current can accurately be produced according to the difference between the internal voltage and the reference voltage.
Due to variations of parameters or misalignment of the mask in the manufacturing process for example, however, a difference arises in threshold voltage between the transistors of the input differential stage, resulting in an offset voltage mainly because of the difference in threshold voltage. The offset voltage represents a deviation of voltage from “virtual short-circuit” state of input terminals of the differential amplifier in an ideal state.
When such an offset voltage exists, the difference between the internal voltage and the reference voltage cannot accurately be detected and thus the internal voltage cannot be maintained at a desired voltage level. Consequently, an operating margin of a load circuit receiving the internal voltage as an operating power supply voltage deteriorates. In particular, for a liquid crystal display device or the like, if the voltage level of a signal driving a gate line, connected to transistors selecting a liquid crystal element, deviates from a target value, a voltage corresponding to display pixel data cannot accurately be generated in the liquid crystal element, resulting in deteriorated display quality.
In addition, a display panel of the liquid crystal device uses a glass substrate as an insulative substrate and accordingly a low-temperature polysilicon TFT (thin film transistor) is employed as a transistor element. Therefore, annealing of the transistor element is insufficient, variation of the threshold voltage attains such a large magnitude as several hundreds mV, and accordingly the magnitude of the offset voltage of the differential amplifier becomes a significant magnitude.
The reference voltage is required of precision. Therefore, the reference voltage is usually generated by a high-precision reference voltage generation circuit based on a power supply voltage. If a required internal voltage is higher than or different in polarity from the reference voltage which can be generated by the reference voltage generation circuit, the internal voltage is level-converted through resistance division for example, to generate a voltage to be compared (hereinafter referred to as comparative voltage) corresponding to the reference voltage level. Further, in order to perform the comparison (differential amplification) in the most sensitive operating region of the differential amplifier, the internal voltage is level-converted (level-shifted) as described above. When the internal voltage is level-converted into a comparative voltage by a resistance division circuit, the offset voltage multiplied by the reciprocal of the resistance division factor is superimposed on the output voltage, resulting in an increased error in comparison/level determination.
Some conventional arts disclose a configuration for suppressing the influences of the offset voltage of the differential amplifier (operational amplifier) on the output voltage, in which the offset voltage is charged and stored on a capacitor and the voltage stored in the capacitor is utilized when operational amplification is performed, to cancel the influence of the offset voltage onto the output voltage. Specifically, in the conventional art, basically the following configuration is employed: the differential amplifier is operated in a voltage follower mode with an input signal being grounded, the capacitor is charged with the output voltage, and the negatively fed back offset voltage is used when differential amplification is performed, to cancel the offset voltage for generating the output voltage.
Specifically, Japanese Patent Laying-Open No. 58-135467 discloses a configuration of a voltage comparison circuit utilizing an operational amplifier. According to this prior art, the differential voltage between two input voltages is sampled by a capacitor, and concurrently, the operational amplifier is operated in the voltage follower mode and an offset voltage relative to a ground voltage is stored in an offset-compensation capacitor. In a comparison operation, the sampling capacitor is connected in series with the offset-compensation capacitor storing the reverse voltage of the offset voltage, a voltage shift of the offset voltage is caused through capacitive coupling in the sampling capacitor and then the potential on one electrode of the sampling capacitor is compared with the ground voltage. The operational amplifier has its positive input grounded, and has its negative input supplied with the voltage at a voltage level having the offset voltage compensated for, and generates a binary signal according to the input signal.
In the configuration of the above-described prior art, two capacitors, or the sampling capacitor for sampling two input voltages and the offset-compensation capacitor for compensating for the offset voltage, are necessary, resulting in an increased area occupied by the level determination section. Further, in the configuration of this prior art, the positive input of the operational amplifier is grounded all the time, the voltage of the signal applied to the negative input is shifted in the reverse direction to the offset voltage, and the signal voltage at the positive input is equivalently shifted by the offset voltage to compensate for the offset. In this prior art, no consideration is given on how the offset voltage is compensated for when the signal is supplied to the positive input. Further, no consideration is given on how the signal indicative of the bi-level determination result is used.
Japanese Patent Laying-Open No. 62-261205 discloses a configuration, in which an operational amplifier is operated in a voltage follower mode, an offset voltage negatively fed back is stored in a capacitance element. A first signal is applied to a positive input and a second signal is transmitted via the capacitance element to a negative input when differential amplification is performed. This prior art merely intends to perform an offset-voltage-compensation upon the differential amplification and gives no consideration on how the output signal is to be used.
Japanese Patent Laying-Open No. 60-142610 discloses a configuration, in which upon detection of an offset voltage, the operational amplifier is operated in the voltage follower mode with differential input being short-circuited and the reference voltage being applied and an output voltage thereof is stored in a capacitance element. When a comparison is made, the differential input is separated to receive a differential signal. In this operation, an input signal is transferred to the negative input via the capacitance element. The configuration of this prior art is similar to that of Japanese Patent Laying-Open No. 62-261205, and gives no consideration on how the output signal is to be used.
Japanese Patent Laying-Open No. 60-198915 discloses that the difference between differential input potentials of a target reference voltage and an input signal is sampled by a sampling capacitance element, and a differential amplifier operates in the voltage follower mode according to a reference power supply voltage from a reference power supply, to store an output signal voltage in a compensation capacitance element. When a comparison is made, one electrode of the sampling capacitor is coupled to the reference power supply, the other electrode of the sampling capacitor is coupled to the negative input of the differential amplifier, and the compensation capacitance element has charge-storing electrode coupled to the reference power supply and the other electrode coupled to the positive input. The sum of the offset voltage and the differential voltage of the differential signal is applied to the differential input, to cancel an influence of the offset of the operational amplifier. In this prior art configuration, the difference between the target reference voltage and the input signal is amplified, and the difference between the reference voltage and the input signal is detected by the sampling capacitor. Therefore, two capacitance elements, or the sampling capacitance element and the offset-compensation capacitance element are required. In addition, this prior art is silent with how the output signal is to be used.
Japanese Patent Laying-Open No. 11-330874 discloses a configuration, in which an operational amplifier is operated in the voltage follower mode, an offset voltage is stored in a level-keeping capacitance element coupled to the negative input, and an input signal is applied to the positive input when amplification is made, to cancel the offset. This prior art merely discloses the use of the operational amplifier as an amplifier at the initial input stage of a radio communication apparatus and is silent with the configuration for using the output signal of the operational amplifier for controlling operations of other circuitry.
Japanese Patent Laying-Open No. 5-129848 discloses a configuration, in which a differential input is short-circuited with a signal of the same voltage level being applied thereto when offset compensation is performed, and current flowing through differential transistors of a differential amplifier is adjusted so that the output signal is equal to a reference voltage (a half power supply voltage). According to this prior art, the voltage corresponding to an input threshold voltage of a circuit in the subsequent stage is used as the reference voltage, and a reference for an offset-compensated voltage is set to a voltage level corresponding to the input threshold voltage of the subsequent circuit. This prior art intends to compensate for the offset voltage of the differential amplifier, but is silent with an operation to be carried out by the circuit in the subsequent stage.
Japanese Patent Laying-Open No. 6-125228 discloses a configuration, in which two-stage differential amplifiers are operated in the voltage follower mode, respective output voltages of the amplifier of the first stage and the amplifier of the second stage are stored in first and second capacitance elements provided at the input and the output of the second-stage differential amplifier. In a comparison operation, the second capacitance element is coupled to the negative input of the first-stage amplifier and a reference voltage is applied to the negative input of the second-stage amplifier. While this prior art also discloses the configuration of compensating for the offset voltage of the differential amplifiers by the voltage stored in the capacitance elements, a reference voltage after D/A conversion is supplied as the reference voltage, and the differential amplifiers are used as comparison circuitry of an A/D conversion circuit of successive comparison type. This prior art reference is silent with the use of the output signal as a control signal for other circuit.
These prior arts as described above give no consideration on the fact that the offset voltage is amplified when the voltage to be compared is level-converted by the resistance-division circuit, and therefore give no consideration on the configuration of suppressing influences of the offset voltage in the case when the offset voltage is amplified.